The present invention relates to a semiconductor device and a manufacturing technology thereof. More particularly, it relates to a technology effectively applicable to a semiconductor device in which a plurality of semiconductor chips are arranged in an array in one package.
Some semiconductor devices come in the form of semiconductor devices using a lead frame called SOP (Small Outline Package).
The SOP includes, for example, as shown in FIG. 2 of Japanese Unexamined Patent Publication No. 2001-24139 (Patent Document 1), a tab (die pad) for mounting a pellet thereon, a plurality of leads respectively arranged on both adjacent sides of the tab (the left-to-right direction of FIG. 2), and tab suspending leads formed integrally with the tab, and led out in the direction in which the leads are not arranged (the top-to-bottom direction of FIG. 2).
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2001-24139